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1 of 47 july 19, 2007 ? 2007 integrated device technology, inc. dsc 6924 idt and the idt logo are registered trademarks of integrated device technology, inc. ? device overview the 89hpes48t12 is a member of the idt precise? family of pci express? switching solutions. the pes48t12 is a 48-lane, 12-port peripheral chip that performs pci express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/network ing. it provides connectivity and switching functions between a pci express upstream port and up to eleven downstream ports and supports switching between downstream ports. features high performance pci express switch ? twelve switch ports ? six main ports each of which consists of 8 serdes ? each x8 main port can further bifurcate to 2 x4-ports ? forty-eight 2.5 gbps embedded serdes ? supports pre-emphasis and receive equalization on per-port basis ? delivers 192 gbps (24 gbps) of aggregate switching capacity ? low-latency cut-through switch architecture ? support for max payload size up to 2048 bytes ? supports one virtual channel and eight traffic classes ? pci express base specification revision 1.1 compliant flexible architecture with nume rous configuration options ? port arbitration schemes utilizing round robin algorithms ? automatic per port link width negotiation to x8, x4, x2 or x1 ? automatic lane reversal on all ports ? automatic polarity inversion on all lanes ? supports locked transactions, allowing use with legacy soft- ware ? ability to load device configuration from serial eeprom ? ability to control device via smbus highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates forty-eight 2.5 gbps embedded full duplex serdes, 8b/10b encoder/decoder (no separate transceivers needed) reliability, availability, and serviceability (ras) features ? redundant upstream port failover capability ? supports optional pci express end-to-end crc checking block diagram figure 1 internal block diagram 48 pci express lanes up to 6 x8 ports or 12 x4 ports 12-port switch core frame buffer route table port arbitration scheduler dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x8/x4/x2/x1 upstream dl/transaction layer serdes x8/x4/x2/x1 dl/transaction layer serdes x8/x4/x2/x1 89hpes48t12 data sheet 48-lane 12-port pci express? switch
2 of 47 july 19, 2007 idt 89hpes48t12 data sheet ? internal end-to-end parity protection on all tlps ensures data integrity even in systems that do not implement end-to-end crc (ecrc) ? supports optional pci express advanced error reporting ? supports pci express hot-plug ? compatible with hot-plug i/o expanders used on pc motherboards ? supports hot-swap power management ? supports pci power management interface specification, revision 1.1 (pci-pm) ? supports powerdown modes at the link level (l0, l0s, l1, l2/l3 ready and l3) and at the device level (d0, d3 hot ) ? unused serdes disabled testability and debug features ? built in serdes pseudo-random bit stream (prbs) generator ? ability to read and write any internal register via the smbus ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters 32 general purpose input/output pins ? each pin may be individually configured as an input or output ? each pin may be individually configured as an interrupt input ? some pins have selectable alternate functions packaged in a 35mm x 35mm 1156- ball flip chip bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes48t12 provides the most efficient connectivity so lution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. it provides 192 gbps of aggregated switching capacity through 48 integrated serial lanes, using proven and robust idt technology. each lane provides 2.5 gbps of bandwidth in both directions and is fully compliant with pci express base specification 1.1. the pes48t12 is based on a flexible and efficient layered architec- ture. the pci express layers consist of serdes, physical, data link and transaction layers. the pes48t12 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and i/o transactions. it supports eight traffic classes (tcs) and one virtual channel (vc) with sophist icated resource management to enable efficient switching and i/o connectivity. smbus interface the pes48t12 contains two smbus interfaces. the slave interface provides full access to the configuration registers in the pes48t12, allowing every configuration register in the device to be read or written by an external agent. the master interface allows the default configura- tion register values of the pes48t12 to be overridden following a reset with values programmed in an external serial eeprom. the master interface is also used by an external hot-plug i/o expander. six pins make up each of the two smbus interfaces. these pins consist of an smbus clock pin, an smbus data pin, and 4 smbus address pins. in the slave interface, these address pins allow the smbus address to which the device responds to be configured. in the master interface, these address pins allow the smbus address of the serial configuration eeprom from which data is loaded to be configured. the smbus address is set up on negation of perstn by sampling the corresponding address pins. when the pi ns are sampled, the resulting address is assigned as shown in table 1. figure 2 port configuration examples note: the configurations in the above diagram s how the maximum port widths. the pes48t12 can negotiate to narrower port widths ? x4, x2, or x1. 0 2 3 5 4 6 7 8 9 10 11 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 x4 x8 x8 x8 x8 x8 x8 1 0 11 10 4 5 8 9 6 7 2 3 non-bifurcated fully bifurcated 1 x4
3 of 47 july 19, 2007 idt 89hpes48t12 data sheet as shown in figure 3, the master and slave smbuses may be used in a unified or split configurati on. in the unified configuratio n, shown in figure 3(a), the master and slave smbuses are tied together and the pes48t12 acts both as a smbus master as well as a smbus slave on t his bus. this requires that the smbus master or processor that has access to pes48t12 registers supports smbus arbitration. in some systems, this smbus master interface may be implemented using general purpose i/o pins on a processor or micro controller, and may not support smbu s arbitration. to support these systems, the pes48t12 may be configured to operat e in a split configuration as shown in figure 3(b). in the split configuration, the master and slave smbuses operat e as two independent buses and thus multi-master arbitration is never required. the pes48t12 supports reading and writing of the serial eeprom on t he master smbus via the slave smbus, allowing in system prog ramming of the serial eeprom. figure 3 smbus interface configuration examples hot-plug interface the pes48t12 supports pci express hot-plug on each downstream port. to reduce the number of pins required on the device, the pe s48t12 utilizes an external i/o expander, such as that used on pc mother boards, connected to the smbus master interface. following res et and configura- tion, whenever the state of a hot-plug output needs to be modifi ed, the pes48t12 generates an smbus transaction to the i/o expa nder with the new value of all of the outputs. whenever a hot-plug input changes, the i/o expander generates an interrupt which is received on th e ioexpintn input pin (alternate function of gpio) of the pes48t12. in response to an i/o expander interrupt, the pes48t12 generates an smbus transac tion to read the state of all of the hot-plug inputs from the i/o expander. general purpose input/output the pes48t12 provides 32 general purpose i/o (gpio) pins that may be individually configured as general purpose inputs, general purpose outputs, or alternate functions. some gpio pins are shared wi th other on-chip functions. these alternate functions may be enabl ed via software, smbus slave interface, or serial configuration eeprom. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbaddr[1] 2 ssmbaddr[2] msmbaddr[2] 3 ssmbaddr[3] msmbaddr[3] 4 0 msmbaddr[4] 5 ssmbaddr[5] 1 61 0 71 1 table 1 master and slave smbus address assignment processor pes48t12 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom processor pes48t12 ssmbclk ssmbdat msmbclk msmbdat smbus master other smbus devices serial eeprom ... ... (a) unified configuration and management bus (b) split configuration and management buses
4 of 47 july 19, 2007 idt 89hpes48t12 data sheet pin description the following tables lists the functions of the pins provided on the pes48t12. some of the functions listed may be multiplexed onto the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select li nes) will be interpreted as being active, or asserted, when at a logic one (high) level. differ- ential signals end with a suffix ?n? or ?p.? the differential si gnal ending in ?p? is the positive portion of the differential pair and the differential signal ending in ?n? is the negative porti on of the differential pair. signal type name/description pe0rp[3:0] pe0rn[3:0] i pci express port 0 serial data receive. differential pci express receive pairs for port 0. port 0 is the upstream port. pe0tp[3:0] pe0tn[3:0] o pci express port 0 serial data transmit. differential pci express transmit pairs for port 0. port 0 is the upstream port. pe1rp[3:0] pe1rn[3:0] i pci express port 1 serial data receive. differential pci express receive pairs for port 1. when port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. pe1tp[3:0] pe1tn[3:0] o pci express port 1 serial data transmit. differential pci express transmit pairs for port 1. when port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. pe2rp[3:0] pe2rn[3:0] i pci express port 2 serial data receive. differential pci express receive pairs for port 2. pe2tp[3:0] pe2tn[3:0] o pci express port 2 serial data transmit. differential pci express transmit pairs for port 2. pe3rp[3:0] pe3rn[3:0] i pci express port 3 serial data receive. differential pci express receive pairs for port 3. when port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. pe3tp[3:0] pe3tn[3:0] o pci express port 3 serial data transmit. differential pci express transmit pairs for port 2. when port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. pe4rp[3:0] pe4rn[3:0] i pci express port 4 serial data receive. differential pci express receive pairs for port 4. pe4tp[3:0] pe4tn[3:0] o pci express port 4 serial data transmit. differential pci express transmit pairs for port 4. pe5rp[3:0] pe5rn[3:0] i pci express port 5 serial data receive. differential pci express receive pairs for port 5. when port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. pe5tp[3:0] pe5tn[3:0] o pci express port 5 serial data transmit. differential pci express transmit pairs for port 5. when port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. pe6rp[3:0] pe6rn[3:0] i pci express port 6 serial data receive. differential pci express receive pairs for port 6. pe6tp[3:0] pe6tn[3:0] o pci express port 6 serial data transmit. differential pci express transmit pairs for port 6. pe7rp[3:0] pe7rn[3:0] i pci express port 7 serial data receive. differential pci express receive pairs for port 7. when port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. table 2 pci express interface pins (part 1 of 2)
5 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe7tp[3:0] pe7tn[3:0] o pci express port 7 serial data transmit. differential pci express transmit pairs for port 7. when port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. pe8rp[3:0] pe8rn[3:0] i pci express port 8 serial data receive. differential pci express receive pairs for port 8. pe8tp[3:0] pe8tn[3:0] o pci express port 8 serial data transmit. differential pci express transmit pairs for port 8. pe9rp[3:0] pe9rn[3:0] i pci express port 9 serial data receive. differential pci express receive pairs for port 9. when port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. pe9tp[3:0] pe9tn[3:0] o pci express port 9 serial data transmit. differential pci express transmit pairs for port 9. when port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. pe10rp[3:0] pe10rn[3:0] i pci express port 10 serial data receive. differential pci express receive pairs for port 10. pe10tp[3:0] pe10tn[3:0] o pci express port 10 serial data transmit. differential pci express transmit pairs for port 10. pe11rp[3:0] pe11rn[3:0] i pci express port 11 serial data receive. differential pci express receive pairs for port 11. when port 10 is merged with port 11, these signals become port 10 receive pairs for lanes 4 through 7. pe11tp[3:0] pe11tn[3:0] o pci express port 11 serial data transmit. differential pci express transmit pairs for port 11. when port 10 is merged with port 11, these signals become port 10 trans- mit pairs for lanes 4 through 7. refclkm i pci express reference clock mode select. this signal selects the frequency of the reference clock input. 0x0 - 100 mhz 0x1 - 125 mhz refclkp[3:0] refclkn[3:0] i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the differential reference clock is determined by the refclkm signal. signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expanders are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the master smbus. table 3 smbus interface pins (part 1 of 2) signal type name/description table 2 pci express interface pins (part 2 of 2)
6 of 47 july 19, 2007 idt 89hpes48t12 data sheet ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize transfers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: gpen alternate function pin type: output alternate function: general purpose event (gpe) output gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p1rstn alternate function pin type: output alternate function: reset output for downstream port 1 gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p2rstn alternate function pin type: output alternate function: reset output for downstream port 2 gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p3rstn alternate function pin type: output alternate function: reset output for downstream port 3 gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p4rstn alternate function pin type: output alternate function: reset output for downstream port 4 table 4 general purpose i/o pins (part 1 of 3) signal type name/description table 3 smbus interface pins (part 2 of 2)
7 of 47 july 19, 2007 idt 89hpes48t12 data sheet gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p5rstn alternate function pin type: output alternate function: reset output for downstream port 5 gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p6rstn alternate function pin type: output alternate function: reset output for downstream port 6 gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p7rstn alternate function pin type: output alternate function: reset output for downstream port 7 gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p8rstn alternate function pin type: output alternate function: reset output for downstream port 8 gpio[14] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p9rstn alternate function pin type: output alternate function: reset output for downstream port 9 gpio[15] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p10rstn alternate function pin type: output alternate function: reset output for downstream port 10 gpio[16] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: p11rstn alternate function pin type: output alternate function: reset output for downstream port 11 gpio[17] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[18] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[19] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[20] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[21] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn0 alternate function pin type: input alternate function: smbus i/o expander interrupt 0 signal type name/description table 4 general purpose i/o pins (part 2 of 3)
8 of 47 july 19, 2007 idt 89hpes48t12 data sheet gpio[22] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn1 alternate function pin type: input alternate function: smbus i/o expander interrupt 1 gpio[23] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn2 alternate function pin type: input alternate function: smbus i/o expander interrupt 2 gpio[24] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn3 alternate function pin type: input alternate function: smbus i/o expander interrupt 3 gpio[25] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn4 alternate function pin type: input alternate function: smbus i/o expander interrupt 4 gpio[26] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: ioexpintn5 alternate function pin type: input alternate function: smbus i/o expander interrupt 5 gpio[27] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[28] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[29] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[30] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[31] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pi n name: ioexpintn10 alternate function pin type: input alternate function: smbus i/o expander interrupt 10. signal type name/description cclkds i common clock downstream. when the cclkds pin is asserted, it indicates that a common clock is being used between the downstream device and the downstream port. cclkus i common clock upstream. when the cclkus pin is asserted, it indicates that a common clock is being used between the upstream device and the upstream port. msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. table 5 system pins (part 1 of 2) signal type name/description table 4 general purpose i/o pins (part 3 of 3)
9 of 47 july 19, 2007 idt 89hpes48t12 data sheet p01mergen i port 0 and 1 merge. when this pin is asserted, port 1 is merged with port 0 to form a single x8 port. the serdes lanes associated with port 1 become lanes 4 through 7 of port 0. p23mergen i port 2 and 3 merge. when this pin is asserted, port 3 is merged with port 2 to form a single x8 port. the serdes lanes associated with port 3 become lanes 4 through 7 of port 2. p45mergen i port 4 and 5 merge. when this pin is asserted, port 5 is merged with port 4 to form a single x8 port. the serdes lanes associated with port 5 become lanes 4 through 7 of port 4. p67mergen i port 6 and 7 merge. when this pin is asserted, port 7 is merged with port 6 to form a single x8 port. the serdes lanes associated with port 7 become lanes 4 through 7 of port 6. p89mergen i port 8 and 9 merge. when this pin is asserted, port 9 is merged with port 8 to form a single x8 port. the serdes lanes associated with port 9 become lanes 4 through 7 of port 8. p1011mergen i port 10 and 11 merge. when this pin is asserted, port 11 is merged with port 10 to form a single x8 port. the serdes lanes associated with port 11 become lanes 4 through 7 of port 10. perstn i fundamental reset. assertion of this signal resets all logic inside the pes48t12 and initiates a pci express fundamental reset. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, pes48t12 executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device operation begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the pes48t12 switch operating mode. 0x0 - normal switch mode 0x1 - normal switch mode with serial eeprom initialization 0x2 through 0x7 - reserved 0x8 - normal switch mode with upstream port failover (port 0 selected as the upstream port) 0x9 - normal switch mode with upstream port failover (port 2 selected as the upstream port) 0xa - normal switch mode with serial eeprom initialization and upstream port failover (port 0 selected as the upstream port) 0xb - normal switch mode with serial eeprom initialization and upstream port failover (port 2 selected as the upstream port) 0xc through 0xf - reserved signal type name/description table 5 system pins (part 2 of 2)
10 of 47 july 19, 2007 idt 89hpes48t12 data sheet signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board table 6 test pins signal type name/description v dd core i core vdd. power supply for core logic. v dd io i i/o vdd. lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. v dd ape i pci express analog power. pci express analog power used by the pll and bias generator. v ss i ground. v tt pe i pci express serial data transmit termination voltage. this pin allows the driver termination voltage to be set, enabling the system designer to control the common mode voltage and output voltage swing of the corresponding pci serial data transmit differential pair. table 7 power and ground pins
11 of 47 july 19, 2007 idt 89hpes48t12 data sheet pin characteristics note: some input pads of the pes48t12 do not contain internal pull- ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially critical for unused control signal i nputs which, if left floating, could adversely affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor notes pci express interface pe0rn[3:0] i cml serial link pe0rp[3:0] i pe0tn[3:0] o pe0tp[3:0] o pe1rn[3:0] i pe1rp[3:0] i pe1tn[3:0] o pe1tp[3:0] o pe2rn[3:0] i pe2rp[3:0] i pe2tn[3:0] o pe2tp[3:0] o pe3rn[3:0] i pe3rp[3:0] i pe3tn[3:0] o pe3tp[3:0] o pe4rn[3:0] i pe4rp[3:0] i pe4tn[3:0] o pe4tp[3:0] o pe5rn[3:0] i pe5rp[3:0] i pe5tn[3:0] o pe5tp[3:0] o pe6rn[3:0] i pe6rp[3:0] i pe6tn[3:0] o pe6tp[3:0] o pe7rn[3:0] i pe7rp[3:0] i pe7tn[3:0] o pe7tp[3:0] o table 8 pin characteristics (part 1 of 3)
12 of 47 july 19, 2007 idt 89hpes48t12 data sheet pci express interface (cont.) pe8rn[3:0] i cml serial link pe8rp[3:0] i pe8tn[3:0] o pe8tp[3:0] o pe9rn[3:0] i pe9rp[3:0] i pe9tn[3:0] o pe9tp[3:0] o pe10rn[3:0] i pe10rp[3:0] i pe10tn[3:0] o pe10tp[3:0] o pe11rn[3:0] i pe11rp[3:0] i pe11tn[3:0] o pe11tp[3:0] o perefclkn[3:0] i lvpecl/ cml diff. clock input refer to table 9 perefclkp[3:0] i refclkm i lvttl input pull-down smbus interface msmbaddr[4:1] i lvttl sti 1 pull-up msmbclk i/o sti msmbdat i/o sti ssmbaddr[5,3:1] i pull-up ssmbclk i/o sti ssmbdat i/o sti general purpose i/o gpio[31:0] i/o lvttl pull-up system pins cclkds i lvttl input pull-up cclkus i pull-up msmbsmode i pull-down p01mergen i pull-down p23mergen i pull-down p45mergen i pull-down p67mergen i pull-down p89mergen i pull-down p1011mergen i pull-down perstn i rsthalt i pull-down swmode[3:0] i pull-down function pin name type buffer i/o type internal resistor notes table 8 pin characteristics (part 2 of 3)
13 of 47 july 19, 2007 idt 89hpes48t12 data sheet ejtag / jtag jtag_tck i lvttl sti pull-up jtag_tdi i sti pull-up jtag_tdo o jtag_tms i sti pull-up jtag_trst_n i sti pull-up external pull-down 1. schmitt trigger input (sti) . function pin name type buffer i/o type internal resistor notes table 8 pin characteristics (part 3 of 3)
14 of 47 july 19, 2007 idt 89hpes48t12 data sheet logic diagram ? pes48t12 figure 4 pes48t12 logic diagram ... reference clock perefclkp[3:0] perefclkn[3:0] jtag_tck gpio[31:0] 32 general purpose i/o v dd core v dd io v dd pe v dd pea power/ground msmbaddr[4:1] msmbclk msmbdat 4 master smbus interface cclkus rsthalt system pins jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag pins v ss swmode[3:0] 4 4 4 cclkds perstn refclkm msmbsmode v tt pe pe0rp[0] pe0rn[0] pe0rp[3] pe0rn[3] pci express switch serdes input pe0tp[0] pe0tn[0] pe0tp[3] pe0tn[3] pci express switch serdes output ... port 0 port 0 ... pe1rp[0] pe1rn[0] pe1rp[3] pe1rn[3] pci express switch serdes input pe1tp[0] pe1tn[0] pe1tp[3] pe1tn[3] pci express switch serdes output ... port 1 port 1 ... pe2rp[0] pe2rn[0] pe2rp[3] pe2rn[3] pci express switch serdes input pe2tp[0] pe2tn[0] pe2tp[3] pe2tn[3] pci express switch serdes output ... port 2 port 2 ... pe3rp[0] pe3rn[0] pe3rp[3] pe3rn[3] pci express switch serdes input pe3tp[0] pe3tn[0] pe3tp[3] pe3tn[3] pci express switch serdes output ... port 3 port 3 ... pe11rp[0] pe11rn[0] pe11rp[3] pe11rn[3] pci express switch serdes input pe11tp[0] pe11tn[0] pe11tp[3] pe11tn[3] pci express switch serdes output ... port 11 port 11 ... pes48t12 ... p01mergen p23mergen p45mergen p67mergen ssmbaddr[5,3:1] ssmbclk ssmbdat 4 slave smbus interface p89mergen p1011mergen
15 of 47 july 19, 2007 idt 89hpes48t12 data sheet system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 13 and 14. ac timing characteristics parameter description min typical max unit perefclk refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal refclkm. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) refers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps table 9 input clock requirements parameter description min 1 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1 typical 1 max 1 units pcie transmit ui unit interval 399.88 400 400.12 ps t tx-eye minimum tx eye width 0.7 .9 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui t tx-rise , t tx-fall d+ / d- tx output rise/fall time 50 90 ps t tx- idle-min minimum time in idle 50 ui t tx-idle-set-to- idle maximum time to transition to a valid idle after sending an idle ordered set 20 ui t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 20 ui t tx-skew transmitter data skew between any 2 lanes 500 1300 ps pcie receive ui unit interval 399.88 400 400.12 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-idle-det-diff- enter time unexpected idle enter detect threshold integration time 10 ms t rx-skew lane to lane input skew 20 ns table 10 pcie ac timing characteristics
16 of 47 july 19, 2007 idt 89hpes48t12 data sheet figure 5 gpio ac timing waveform signal symbol reference edge min max unit timing diagram reference gpio gpio[31:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns see figure 5. table 11 gpio ac timing characteristics signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 6. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n chang - es from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag_tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset state. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 12 jtag ac timing characteristics tpw_13b extclk gpio (asynchronous input)
17 of 47 july 19, 2007 idt 89hpes48t12 data sheet figure 6 jtag ac timing waveform recommended operating supply voltages power-up sequence this section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. for the pes48t12, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd ape ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prio r to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power levels. the power-down sequence must be in the rev erse order of the power-up sequence. symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes lvpecl/cml 3.0 3.3 3.6 v v dd pe pci express digital power 0.9 1.0 1.1 v v dd ape pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termination voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 13 pes48t12 operating voltages tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
18 of 47 july 19, 2007 idt 89hpes48t12 data sheet recommended operating temperature power consumption typical power is measured under the following conditions: 25c ambient, 35% total link usage on all ports, typical voltages def ined in table 13 (and also listed below). maximum power is measured under the following conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 13 (and also listed below). grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 14 pes48t12 operating temperatures number of active lanes per port core supply pcie digital supply pcie analog supply pcie termin- ation supply i/o supply total typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.0v max 1.1v typ 1.5v max 1.575v typ 3.3v max 3.6v typ power max power 8/8/8/8/8/8 ma 2141 2635 2155 2657 918 1127 1076 1327 3.8 3.8 6.85w 9.16w watts 2.14 2.89 2.15 2.92 0.91 1.24 1.6 2.09 0.01 0.01 table 15 pes48t12 power consumption
19 of 47 july 19, 2007 idt 89hpes48t12 data sheet thermal considerations this section describes thermal considerations for the pes48t12 (35mm 2 fcbga1156 package). the data in table 16 below contains information that is relevant to the thermal performance of the pes48t12 switch. note: it is important for the reliability of this device in any us er environment that the junction temperature not exceed the t j(max) value specified in table 16. consequently, the effectiv e junction to ambient thermal resistance ( ja ) for the worst case scenario must be maintained below the value determined by the formula: ja = (t j(max) - t a(max) )/p given that the values of t j(max) , t a(max) , and p are known, the value of desired ja becomes a known entity to the system designer. how to achieve the desired ja is left up to the board or system designer, but in general, it can be achieved by adding the effects of jc (value provided in table 16), thermal resistance of the chosen adhesive ( cs ), that of the heat sink ( sa ), amount of airflow, and properties of the circuit board (number of layers and size of the board). as a general guideline, this device will not need a heat sink if the bo ard has 10 or more layers and the board size is larger than 4"x12" and airf low in excess of 1 m/s is available. it is strongly recommended th at users perform their own thermal analysis for their own board and system design scenarios. symbol parameter value units conditions t j(max) junction temperature 125 o c maximum t a(max) ambient temperature 70 o c maximum jc thermal resistance, junction-to-case 0.2 o c/w p power dissipation of the device 9.16 watts maximum table 16 thermal specifications for pes48t12, 35x35 mm fcbga1156 package
20 of 47 july 19, 2007 idt 89hpes48t12 data sheet dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 13. note: see table 8, pin characteristics, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 17 dc electrical characteristics (part 1 of 2)
21 of 47 july 19, 2007 idt 89hpes48t12 data sheet other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ? 12.0 ? ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.0a. i/o type parameter description min 1 typ 1 max 1 unit conditions table 17 dc electrical characteristics (part 2 of 2)
22 of 47 july 19, 2007 idt 89hpes48t12 data sheet package pinout ? 1156-bga signal pinout for pes48t12 the following table lists the pin numbers and signal names for the pes48t12 device. pin function alt pin function alt pin function alt pin function alt a1 v ss b1 v ss c1 gpio_29 d1 gpio_28 a2 v ss b2 v dd io c2 gpio_27 d2 gpio_26 1 a3 gpio_19 b3 gpio_18 c3 gpio_21 1 d3 v dd io a4 v dd io b4 gpio_17 c4 gpio_16 1 d4 gpio_23 1 a5 v ss b5 v ss c5 v ss d5 v ss a6 pe9tp03 b6 pe9tn03 c6 v ss d6 pe9rp03 a7 pe9tp02 b7 pe9tn02 c7 v ss d7 pe9rp02 a8 v ss b8 v ss c8 v ss d8 v ss a9 pe9tp01 b9 pe9tn01 c9 v ss d9 pe9rp01 a10 pe9tp00 b10 pe9tn00 c10 v ss d10 pe9rp00 a11 v ss b11 v ss c11 v ss d11 v ss a12 pe8tp03 b12 pe8tn03 c12 v ss d12 pe8rp03 a13 pe8tp02 b13 pe8tn02 c13 v ss d13 pe8rp02 a14 v ss b14 v ss c14 v ss d14 v ss a15 pe8tp01 b15 pe8tn01 c15 v ss d15 pe8rp01 a16 pe8tp00 b16 pe8tn00 c16 v ss d16 pe8rp00 a17 v ss b17 v ss c17 v ss d17 v ss a18 pe3tp03 b18 pe3tn03 c18 v ss d18 pe3rp03 a19 pe3tp02 b19 pe3tn02 c19 v ss d19 pe3rp02 a20 v ss b20 v ss c20 v ss d20 v ss a21 pe3tp01 b21 pe3tn01 c21 v ss d21 pe3rp01 a22 pe3tp00 b22 pe3tn00 c22 v ss d22 pe3rp00 a23 v ss b23 v ss c23 v ss d23 v ss a24 pe2tp03 b24 pe2tn03 c24 v ss d24 pe2rp03 a25 pe2tp02 b25 pe2tn02 c25 v ss d25 pe2rp02 a26 v ss b26 v ss c26 v ss d26 v ss a27 pe2tp01 b27 pe2tn01 c27 v ss d27 pe2rp01 a28 pe2tp00 b28 pe2tn00 c28 v ss d28 pe2rp00 a29 v ss b29 v ss c29 v ss d29 v ss a30 v dd io b30 msmbaddr_3 c30 msmbaddr_4 d30 jtag_tms a31 msmbaddr_1 b31 msmbaddr_2 c31 jtag_tdi d31 v dd io a32 msmbsmode b32 perstn c32 jtag_trst_n d32 ssmbaddr_5 a33 v ss b33 v dd io c33 ssmbaddr_2 d33 ssmbaddr_3 a34 v ss b34 v ss c34 ssmbaddr_1 d34 v dd io table 18 pes48t12 1156-pin signal pin-out (part 1 of 9)
23 of 47 july 19, 2007 idt 89hpes48t12 data sheet e1 v dd io f1 v ss g1 pe10tp00 h1 pe10tp01 e2 gpio_30 f2 v ss g2 pe10tn00 h2 pe10tn01 e3 gpio_31 1 f3 v ss g3 v ss h3 v ss e4 gpio_24 1 f4 v ss g4 pe10rp00 h4 pe10rp01 e5 v ss f5 v ss g5 pe10rn00 h5 pe10rn01 e6 pe9rn03 f6 v ss g6 v ss h6 v ss e7 pe9rn02 f7 v ss g7 v ss h7 v ss e8 v ss f8 v ss g8 v ss h8 gpio_20 e9 pe9rn01 f9 v ss g9 v ss h9 v dd io e10 pe9rn00 f10 v ss g10 v ss h10 v ss e11 v ss f11 v ss g11 v ss h11 v ss e12 pe8rn03 f12 v ss g12 v ss h12 v ss e13 pe8rn02 f13 v ss g13 v ss h13 v tt pe e14 v ss f14 v ss g14 v ss h14 v ss e15 pe8rn01 f15 v ss g15 v ss h15 v dd ape e16 pe8rn00 f16 v ss g16 v ss h16 v ss e17 v ss f17 v ss g17 perefclkp1 h17 v ss e18 pe3rn03 f18 v ss g18 perefclkn1 h18 v ss e19 pe3rn02 f19 v ss g19 v ss h19 v ss e20 v ss f20 v ss g20 v ss h20 v dd ape e21 pe3rn01 f21 v ss g21 v ss h21 v ss e22 pe3rn00 f22 v ss g22 v ss h22 v tt pe e23 v ss f23 v ss g23 v ss h23 v ss e24 pe2rn03 f24 v ss g24 v ss h24 v ss e25 pe2rn02 f25 v ss g25 v ss h25 v ss e26 v ss f26 v ss g26 v ss h26 msmbdat e27 pe2rn01 f27 v ss g27 msmbclk h27 v dd io e28 pe2rn00 f28 v ss g28 v ss h28 ssmbclk e29 v ss f29 v ss g29 v ss h29 v ss e30 v ss f30 pe1rn03 g30 pe1rn02 h30 v ss e31 v ss f31 pe1rp03 g31 pe1rp02 h31 v ss e32 v ss f32 v ss g32 v ss h32 v ss e33 v ss f33 pe1tn03 g33 pe1tn02 h33 v ss e34 v ss f34 pe1tp03 g34 pe1tp02 h34 v ss pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 2 of 9)
24 of 47 july 19, 2007 idt 89hpes48t12 data sheet j1 v ss k1 pe10tp02 l1 pe10tp03 m1 v ss j2 v ss k2 pe10tn02 l2 pe10tn03 m2 v ss j3 v ss k3 v ss l3 v ss m3 v ss j4 v ss k4 pe10rp02 l4 pe10rp03 m4 v ss j5 v ss k5 pe10rn02 l5 pe10rn03 m5 v ss j6 v ss k6 v ss l6 v ss m6 v ss j7 v ss k7 v ss l7 v ss m7 v ss j8 v ss k8 v ss l8 v ss m8 v ss j9 gpio_25 1 k9 v dd io l9 v ss m9 v ss j10 v ss k10 gpio_22 1 l10 v ss m10 v ss j11 v ss k11 v ss l11 v ss m11 v ss j12 v ss k12 v ss l12 v ss m12 v ss j13 v ss k13 v tt pe l13 v dd pe m13 v dd pe j14 v dd pe k14 v ss l14 v dd pe m14 v ss j15 v ss k15 v dd ape l15 v dd pe m15 v dd pe j16 v ss k16 v ss l16 v ss m16 v ss j17 v tt pe k17 v tt pe l17 v dd pe m17 v dd pe j18 v tt pe k18 v tt pe l18 v dd pe m18 v dd pe j19 v ss k19 v ss l19 v ss m19 v ss j20 v ss k20 v dd ape l20 v dd pe m20 v dd pe j21 v dd pe k21 v ss l21 v dd pe m21 v ss j22 v ss k22 v tt pe l22 v dd pe m22 v dd pe j23 v ss k23 v ss l23 v ss m23 v ss j24 v ss k24 v ss l24 v ss m24 v ss j25 jtag_tdo k25 cclkds l25 v ss m25 v ss j26 v dd io k26 jtag_tck l26 v ss m26 v ss j27 ssmbdat k27 v ss l27 v ss m27 v ss j28 v ss k28 v ss l28 v ss m28 v ss j29 v ss k29 v ss l29 v ss m29 v ss j30 pe1rn01 k30 pe1rn00 l30 v ss m30 pe0rn03 j31 pe1rp01 k31 pe1rp00 l31 v ss m31 pe0rp03 j32 v ss k32 v ss l32 v ss m32 v ss j33 pe1tn01 k33 pe1tn00 l33 v ss m33 pe0tn03 j34 pe1tp01 k34 pe1tp00 l34 v ss m34 pe0tp03 pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 3 of 9)
25 of 47 july 19, 2007 idt 89hpes48t12 data sheet n1 pe11tp00 p1 pe11tp01 r1 v ss t1 pe11tp02 n2 pe11tn00 p2 pe11tn01 r2 v ss t2 pe11tn02 n3 v ss p3 v ss r3 v ss t3 v ss n4 pe11rp00 p4 pe11rp01 r4 v ss t4 pe11rp02 n5 pe11rn00 p5 pe11rn01 r5 v ss t5 pe11rn02 n6 v ss p6 v ss r6 v ss t6 v ss n7 v ss p7 v ss r7 v ss t7 v ss n8 v tt pe p8 v ss r8 v dd ape t8 v ss n9 v ss p9 v dd pe r9 v ss t9 v ss n10 v tt pe p10 v ss r10 v dd ape t10 v ss n11 v dd pe p11 v dd pe r11 v dd pe t11 v ss n12 v dd pe p12 v ss r12 v dd pe t12 v ss n13 v dd core p13 v dd core r13 v dd core t13 v ss n14 v dd core p14 v ss r14 v dd core t14 v ss n15 v dd core p15 v dd core r15 v ss t15 v dd core n16 v ss p16 v ss r16 v dd core t16 v ss n17 v dd core p17 v dd core r17 v ss t17 v dd core n18 v ss p18 v ss r18 v dd core t18 v ss n19 v dd core p19 v dd core r19 v ss t19 v dd core n20 v dd core p20 v ss r20 v dd core t20 v ss n21 v dd core p21 v dd core r21 v ss t21 v dd core n22 v dd core p22 v dd core r22 v dd core t22 v dd core n23 v dd pe p23 v ss r23 v dd pe t23 v ss n24 v dd pe p24 v dd pe r24 v dd pe t24 v ss n25 v tt pe p25 v ss r25 v dd ape t25 v ss n26 v ss p26 v dd pe r26 v ss t26 v ss n27 v tt pe p27 v ss r27 v dd ape t27 v ss n28 v ss p28 v ss r28 v ss t28 v ss n29 v ss p29 v ss r29 v ss t29 v ss n30 pe0rn02 p30 v ss r30 pe0rn01 t30 pe0rn00 n31 pe0rp02 p31 v ss r31 pe0rp01 t31 pe0rp00 n32 v ss p32 v ss r32 v ss t32 v ss n33 pe0tn02 p33 v ss r33 pe0tn01 t33 pe0tn00 n34 pe0tp02 p34 v ss r34 pe0tp01 t34 pe0tp00 pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 4 of 9)
26 of 47 july 19, 2007 idt 89hpes48t12 data sheet u1 pe11tp03 v1 v ss w1 pe4tp00 y1 pe4tp01 u2 pe11tn03 v2 v ss w2 pe4tn00 y2 pe4tn01 u3 v ss v3 v ss w3 v ss y3 v ss u4 pe11rp03 v4 v ss w4 pe4rp00 y4 pe4rp01 u5 pe11rn03 v5 v ss w5 pe4rn00 y5 pe4rn01 u6 v ss v6 v ss w6 v ss y6 v ss u7 perefclkn2 v7 perefclkp2 w7 v ss y7 v ss u8 v ss v8 v ss w8 v ss y8 v dd ape u9 v tt pe v9 v tt pe w9 v ss y9 v ss u10 v tt pe v10 v tt pe w10 v ss y10 v dd ape u11 v dd pe v11 v dd pe w11 v ss y11 v dd pe u12 v dd pe v12 v dd pe w12 v ss y12 v dd pe u13 v dd core v13 v ss w13 v dd core y13 v dd core u14 v dd core v14 v ss w14 v dd core y14 v ss u15 v ss v15 v dd core w15 v ss y15 v dd core u16 v dd core v16 v ss w16 v dd core y16 v ss u17 v ss v17 v dd core w17 v ss y17 v dd core u18 v dd core v18 v ss w18 v dd core y18 v ss u19 v ss v19 v dd core w19 v ss y19 v dd core u20 v dd core v20 v ss w20 v dd core y20 v ss u21 v ss v21 v dd core w21 v ss y21 v dd core u22 v ss v22 v dd core w22 v ss y22 v dd core u23 v dd pe v23 v dd pe w23 v ss y23 v dd pe u24 v dd pe v24 v dd pe w24 v ss y24 v dd pe u25 v tt pe v25 v tt pe w25 v ss y25 v dd ape u26 v tt pe v26 v tt pe w26 v ss y26 v ss u27 v ss v27 v ss w27 v ss y27 v dd ape u28 perefclkp0 v28 perefclkn0 w28 v ss y28 v ss u29 v ss v29 v ss w29 v ss y29 v ss u30 v ss v30 nc w30 nc y30 v ss u31 v ss v31 nc w31 nc y31 v ss u32 v ss v32 v ss w32 v ss y32 v ss u33 v ss v33 nc w33 nc y33 v ss u34 v ss v34 nc w34 nc y34 v ss pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 5 of 9)
27 of 47 july 19, 2007 idt 89hpes48t12 data sheet aa1 v ss ab1 pe4tp02 ac1 pe4tp03 ad1 v ss aa2 v ss ab2 pe4tn02 ac2 pe4tn03 ad2 v ss aa3 v ss ab3 v ss ac3 v ss ad3 v ss aa4 v ss ab4 pe4rp02 ac4 pe4rp03 ad4 v ss aa5 v ss ab5 pe4rn02 ac5 pe4rn03 ad5 v ss aa6 v ss ab6 v ss ac6 v ss ad6 v ss aa7 v ss ab7 v ss ac7 v ss ad7 v ss aa8 v ss ab8 v tt pe ac8 v ss ad8 v ss aa9 v dd pe ab9 v ss ac9 v ss ad9 v ss aa10 v ss ab10 v tt pe ac10 v ss ad10 v ss aa11 v dd pe ab11 v dd pe ac11 v ss ad11 v ss aa12 v ss ab12 v dd pe ac12 v ss ad12 v ss aa13 v dd core ab13 v dd core ac13 v dd pe ad13 v dd pe aa14 v dd core ab14 v dd core ac14 v ss ad14 v dd pe aa15 v ss ab15 v dd core ac15 v dd pe ad15 v dd pe aa16 v dd core ab16 v dd core ac16 v ss ad16 v ss aa17 v ss ab17 v ss ac17 v dd pe ad17 v dd pe aa18 v dd core ab18 v dd core ac18 v dd pe ad18 v dd pe aa19 v ss ab19 v ss ac19 v ss ad19 v ss aa20 v dd core ab20 v dd core ac20 v dd pe ad20 v dd pe aa21 v ss ab21 v dd core ac21 v ss ad21 v dd pe aa22 v dd core ab22 v dd core ac22 v dd pe ad22 v dd pe aa23 v ss ab23 v dd pe ac23 v ss ad23 v ss aa24 v dd pe ab24 v dd pe ac24 v ss ad24 v ss aa25 v ss ab25 v tt pe ac25 v ss ad25 v ss aa26 v dd pe ab26 v ss ac26 v ss ad26 v ss aa27 v ss ab27 v tt pe ac27 v ss ad27 v ss aa28 v ss ab28 v ss ac28 v ss ad28 v ss aa29 v ss ab29 v ss ac29 v ss ad29 v ss aa30 nc ab30 nc ac30 v ss ad30 nc aa31 nc ab31 nc ac31 v ss ad31 nc aa32 v ss ab32 v ss ac32 v ss ad32 v ss aa33 nc ab33 nc ac33 v ss ad33 nc aa34 nc ab34 nc ac34 v ss ad34 nc pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 6 of 9)
28 of 47 july 19, 2007 idt 89hpes48t12 data sheet ae1 pe5tp00 af1 pe5tp01 ag1 v ss ah1 pe5tp02 ae2 pe5tn00 af2 pe5tn01 ag2 v ss ah2 pe5tn02 ae3 v ss af3 v ss ag3 v ss ah3 v ss ae4 pe5rp00 af4 pe5rp01 ag4 v ss ah4 pe5rp02 ae5 pe5rn00 af5 pe5rn01 ag5 v ss ah5 pe5rn02 ae6 v ss af6 v ss ag6 v ss ah6 v ss ae7 v ss af7 v ss ag7 cclkus ah7 v ss ae8 v ss af8 v ss ag8 v dd io ah8 refclkm ae9 v dd io af9 v dd io ag9 v dd io ah9 v ss ae10 v ss af10 v ss ag10 v ss ah10 v ss ae11 v ss af11 v ss ag11 v ss ah11 v ss ae12 v ss af12 v ss ag12 v ss ah12 v ss ae13 v tt pe af13 v ss ag13 v tt pe ah13 v ss ae14 v ss af14 v dd pe ag14 v ss ah14 v ss ae15 v dd ape af15 v ss ag15 v dd ape ah15 v ss ae16 v ss af16 v ss ag16 v ss ah16 v ss ae17 v tt pe af17 v tt pe ag17 v ss ah17 perefclkn3 ae18 v tt pe af18 v tt pe ag18 v ss ah18 perefclkp3 ae19 v ss af19 v ss ag19 v ss ah19 v ss ae20 v dd ape af20 v ss ag20 v dd ape ah20 v ss ae21 v ss af21 v dd pe ag21 v ss ah21 v ss ae22 v tt pe af22 v ss ag22 v tt pe ah22 v ss ae23 v ss af23 v ss ag23 v ss ah23 v ss ae24 v ss af24 v ss ag24 v ss ah24 v ss ae25 gpio_06 1 af25 v ss ag25 v ss ah25 v ss ae26 v dd io af26 gpio_09 1 ag26 v dd io ah26 v ss ae27 v ss af27 v ss ag27 gpio_04 ah27 v ss ae28 v ss af28 v ss ag28 v ss ah28 v ss ae29 v ss af29 v ss ag29 v ss ah29 v ss ae30 nc af30 v ss ag30 nc ah30 nc ae31 nc af31 v ss ag31 nc ah31 nc ae32 v ss af32 v ss ag32 v ss ah32 v ss ae33 nc af33 v ss ag33 nc ah33 nc ae34 nc af34 v ss ag34 nc ah34 nc pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 7 of 9)
29 of 47 july 19, 2007 idt 89hpes48t12 data sheet aj1 pe5tp03 ak1 v ss al1 v dd io am1 p23mergen aj2 pe5tn03 ak2 v ss al2 p01mergen am2 p67mergen aj3 v ss ak3 v ss al3 p45mergen am3 v ss aj4 pe5rp03 ak4 v ss al4 v dd io am4 p1011mergen aj5 pe5rn03 ak5 v ss al5 p89mergen am5 swmode_3 aj6 v ss ak6 v ss al6 v ss am6 v ss aj7 v ss ak7 pe6rn00 al7 pe6rp00 am7 v ss aj8 v ss ak8 pe6rn01 al8 pe6rp01 am8 v ss aj9 v ss ak9 v ss al9 v ss am9 v ss aj10 v ss ak10 pe6rn02 al10 pe6rp02 am10 v ss aj11 v ss ak11 pe6rn03 al11 pe6rp03 am11 v ss aj12 v ss ak12 v ss al12 v ss am12 v ss aj13 v ss ak13 pe7rn00 al13 pe7rp00 am13 v ss aj14 v ss ak14 pe7rn01 al14 pe7rp01 am14 v ss aj15 v ss ak15 v ss al15 v ss am15 v ss aj16 v ss ak16 pe7rn02 al16 pe7rp02 am16 v ss aj17 v ss ak17 pe7rn03 al17 pe7rp03 am17 v ss aj18 v ss ak18 v ss al18 v ss am18 v ss aj19 v ss ak19 nc al19 nc am19 v ss aj20 v ss ak20 nc al20 nc am20 v ss aj21 v ss ak21 v ss al21 v ss am21 v ss aj22 v ss ak22 nc al22 nc am22 v ss aj23 v ss ak23 nc al23 nc am23 v ss aj24 v ss ak24 v ss al24 v ss am24 v ss aj25 v ss ak25 nc al25 nc am25 v ss aj26 v ss ak26 nc al26 nc am26 v ss aj27 v ss ak27 v ss al27 v ss am27 v ss aj28 v ss ak28 nc al28 nc am28 v ss aj29 v ss ak29 nc al29 nc am29 v ss aj30 v ss ak30 v ss al30 v ss am30 v ss aj31 v ss ak31 gpio_08 1 al31 gpio_07 1 am31 gpio_00 aj32 v ss ak32 gpio_15 1 al32 v dd io am32 gpio_05 1 aj33 v ss ak33 gpio_14 1 al33 gpio_10 1 am33 gpio_11 1 aj34 v ss ak34 v dd io al34 gpio_12 1 am34 gpio_13 1 pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 8 of 9)
30 of 47 july 19, 2007 idt 89hpes48t12 data sheet alternate signal functions an1 v ss an18 v ss ap1 v ss ap18 v ss an2 v dd io an19 nc ap2 v ss ap19 nc an3 v ss an20 nc ap3 rsthalt ap20 nc an4 swmode_0 an21 v ss ap4 swmode_1 ap21 v ss an5 swmode_2 an22 nc ap5 v dd io ap22 nc an6 v ss an23 nc ap6 v ss ap23 nc an7 pe6tn00 an24 v ss ap7 pe6tp00 ap24 v ss an8 pe6tn01 an25 nc ap8 pe6tp01 ap25 nc an9 v ss an26 nc ap9 v ss ap26 nc an10 pe6tn02 an27 v ss ap10 pe6tp02 ap27 v ss an11 pe6tn03 an28 nc ap11 pe6tp03 ap28 nc an12 v ss an29 nc ap12 v ss ap29 nc an13 pe7tn00 an30 v ss ap13 pe7tp00 ap30 v ss an14 pe7tn01 an31 gpio_01 ap14 pe7tp01 ap31 v dd io an15 v ss an32 gpio_02 ap15 v ss ap32 gpio_03 an16 pe7tn02 an33 v dd io ap16 pe7tp02 ap33 v ss an17 pe7tn03 an34 v ss ap17 pe7tp03 ap34 v ss pin gpio alternate pin gpio alternate am32 gpio_05 gpen ak32 gpio_15 p10rstn ae25 gpio_06 p1rstn c4 gpio_16 p11rstn al31 gpio_07 p2rstn c3 gpio_21 ioexpintn0 ak31 gpio_08 p3rstn k10 gpio_22 ioexpintn1 af26 gpio_09 p4rstn d4 gpio_23 ioexpintn2 al33 gpio_10 p5rstn e4 gpio_24 ioexpintn3 am33 gpio_11 p6rstn j9 gpio_25 ioexpintn4 al34 gpio_12 p7rstn d2 gpio_26 ioexpintn5 am34 gpio_13 p8rstn e3 gpio_31 ioexpintn10 ak33 gpio_14 p9rstn ? ? ? table 19 pes48t12 alternate signal functions pin function alt pin function alt pin function alt pin function alt table 18 pes48t12 1156-pin signal pin-out (part 9 of 9)
31 of 47 july 19, 2007 idt 89hpes48t12 data sheet power pins v dd core v dd core v dd io v dd pe v dd pe v dd ape v tt pe n13 v19 a4 j14 v11 h15 h13 n14 v21 a30 j21 v12 h20 h22 n15 v22 b2 l13 v23 k15 j17 n17 w13 b33 l14 v24 k20 j18 n19 w14 d3 l15 y11 r8 k13 n20 w16 d31 l17 y12 r10 k17 n21 w18 d34 l18 y23 r25 k18 n22 w20 e1 l20 y24 r27 k22 p13 y13 h9 l21 aa9 y8 n8 p15 y15 h27 l22 aa11 y10 n10 p17 y17 j26 m13 aa24 y25 n25 p19 y19 k9 m15 aa26 y27 n27 p21 y21 ae9 m17 ab11 ae15 u9 p22 y22 ae26 m18 ab12 ae20 u10 r13 aa13 af9 m20 ab23 ag15 u25 r14 aa14 ag8 m22 ab24 ag20 u26 r16 aa16 ag9 n11 ac13 y9 r18 aa18 ag26 n12 ac15 v10 r20 aa20 ak34 n23 ac17 v25 r22 aa22 al1 n24 ac18 v26 t15 ab13 al4 p9 ac20 ab8 t17 ab14 al32 p11 ac22 ab10 t19 ab15 an2 p24 ad13 ab25 t21 ab16 an33 p26 ad14 ab27 t22 ab18 ap5 r11 ad15 ae13 u13 ab20 ap31 r12 ad17 ae17 u14 ab21 r23 ad18 ae18 u16 ab22 r24 ad20 ae22 u18 u11 ad21 af17 u20 u12 ad22 af18 v15 u23 af14 ag13 v17 u24 af21 ag22 table 20 pes48t12 power pins
32 of 47 july 19, 2007 idt 89hpes48t12 data sheet ground pins v ss v ss v ss v ss v ss v ss v ss v ss a1 c16 e33 g8 h29 k16 m5 p12 a2 c17 e34 g9 h30 k19 m6 p14 a5 c18 f1 g10 h31 k21 m7 p16 a8 c19 f2 g11 h32 k23 m8 p18 a11 c20 f3 g12 h33 k24 m9 p20 a14 c21 f4 g13 h34 k27 m10 p23 a17 c22 f5 g14 j1 k28 m11 p25 a20 c23 f6 g15 j2 k29 m12 p27 a23 c24 f7 g16 j3 k32 m14 p28 a26 c25 f8 g19 j4 l3 m16 p29 a29 c26 f9 g20 j5 l6 m19 p30 a33 c27 f10 g21 j6 l7 m21 p31 a34 c28 f11 g22 j7 l8 m23 p32 b1 c29 f12 g23 j8 l9 m24 p33 b5 d5 f13 g24 j10 l10 m25 p34 b8 d8 f14 g25 j11 l11 m26 r1 b11 d11 f15 g26 j12 l12 m27 r2 b14 d14 f16 g28 j13 l16 m28 r3 b17 d17 f17 g29 j15 l19 m29 r4 b20 d20 f18 g32 j16 l23 m32 r5 b23 d23 f19 h3 j19 l24 n3 r6 b26 d26 f20 h6 j20 l25 n6 r7 b29 d29 f21 h7 j22 l26 n7 r9 b34 e5 f22 h10 j23 l27 n9 r15 c5 e8 f23 h11 j24 l28 n16 r17 c6 e11 f24 h12 j28 l29 n18 r19 c7 e14 f25 h14 j29 l30 n26 r21 c8 e17 f26 h16 j32 l31 n28 r26 c9 e20 f27 h17 k3 l32 n29 r28 c10 e23 f28 h18 k6 l33 n32 r29 c11 e26 f29 h19 k7 l34 p3 r32 c12 e29 f32 h21 k8 m1 p6 t3 c13 e30 g3 h23 k11 m2 p7 t6 c14 e31 g6 h24 k12 m3 p8 t7 c15 e32 g7 h25 k14 m4 p10 t8 table 21 pes48t12 ground pins (part 1 of 3)
33 of 47 july 19, 2007 idt 89hpes48t12 data sheet t9 v6 y18 ab28 ad11 af15 ah3 aj19 t10 v8 y20 ab29 ad12 af16 ah6 aj20 t11 v13 y26 ab32 ad16 af19 ah7 aj21 t12 v14 y28 ac3 ad19 af20 ah9 aj22 t13 v16 y29 ac6 ad23 af22 ah10 aj23 t14 v18 y30 ac7 ad24 af23 ah11 aj24 t16 v20 y31 ac8 ad25 af24 ah12 aj25 t18 v27 y32 ac9 ad26 af25 ah13 aj26 t20 v29 y33 ac10 ad27 af27 ah14 aj27 t23 v32 y34 ac11 ad28 af28 ah15 aj28 t24 w3 aa1 ac12 ad29 af29 ah16 aj29 t25 w6 aa2 ac14 ad32 af30 ah19 aj30 t26 w7 aa3 ac16 ae3 af31 ah20 aj31 t27 w8 aa4 ac19 ae6 af32 ah21 aj32 t28 w9 aa5 ac21 ae7 af33 ah22 aj33 t29 w10 aa6 ac23 ae8 af34 ah23 aj34 t32 w11 aa7 ac24 ae10 ag1 ah24 ak1 u3 w12 aa8 ac25 ae11 ag2 ah25 ak2 u6 w15 aa10 ac26 ae12 ag3 ah26 ak3 u8 w17 aa12 ac27 ae14 ag4 ah27 ak4 u15 w19 aa15 ac28 ae16 ag5 ah28 ak5 u17 w21 aa17 ac29 ae19 ag6 ah29 ak6 u19 w22 aa19 ac30 ae21 ag10 ah32 ak9 u21 w23 aa21 ac31 ae23 ag11 aj3 ak12 u22 w24 aa23 ac32 ae24 ag12 aj6 ak15 u27 w25 aa25 ac33 ae27 ag14 aj7 ak18 u29 w26 aa27 ac34 ae28 ag16 aj8 ak21 u30 w27 aa28 ad1 ae29 ag17 aj9 ak24 u31 w28 aa29 ad2 ae32 ag18 aj10 ak27 u32 w29 aa32 ad3 af3 ag19 aj11 ak30 u33 w32 ab3 ad4 af6 ag21 aj12 al6 u34 y3 ab6 ad5 af7 ag23 aj13 al9 v1 y6 ab7 ad6 af8 ag24 aj14 al12 v2 y7 ab9 ad7 af10 ag25 aj15 al15 v3 y9 ab17 ad8 af11 ag28 aj16 al18 v4 y14 ab19 ad9 af12 ag29 aj17 al21 v5 y16 ab26 ad10 af13 ag32 aj18 al24 v ss v ss v ss v ss v ss v ss v ss v ss table 21 pes48t12 ground pins (part 2 of 3)
34 of 47 july 19, 2007 idt 89hpes48t12 data sheet no connect pins signals listed alphabetically al27 am10 am17 am24 an1 an21 ap6 ap27 al30 am11 am18 am25 an3 an24 ap9 ap30 am3 am12 am19 am26 an6 an27 ap12 ap33 am6 am13 am20 am27 an9 an30 ap15 ap34 am7 am14 am21 am28 an12 an34 ap18 am8 am15 am22 am29 an15 ap1 ap21 am9 am16 am23 am30 an18 ap2 ap24 nc nc nc nc nc nc nc nc v30 aa31 ad33 ag34 ak25 al26 an28 ap29 v31 aa33 ad34 ah30 ak26 al28 an29 v33 aa34 ae30 ah31 ak28 al29 ap19 v34 ab30 ae31 ah33 ak29 an19 ap20 w30 ab31 ae33 ah34 al19 an20 ap22 w31 ab33 ae34 ak19 al20 an22 ap23 w33 ab34 ag30 ak20 al22 an23 ap25 w34 ad30 ag31 ak22 al23 an25 ap26 aa30 ad31 ag33 ak23 al25 an26 ap28 table 22 pes48t12 no connect pins signal name i/o type location signal category cclkds i k25 system cclkus i ag7 table 23 89pes48t12 alphabetical signal list (part 1 of 9) v ss v ss v ss v ss v ss v ss v ss v ss table 21 pes48t12 ground pins (part 3 of 3)
35 of 47 july 19, 2007 idt 89hpes48t12 data sheet gpio_00 i/o am31 general purpose i/o gpio_01 i/o an31 gpio_02 i/o an32 gpio_03 i/o ap32 gpio_04 i/o ag27 gpio_05 i/o am32 gpio_06 i/o ae25 gpio_07 i/o al31 gpio_08 i/o ak31 general purpose i/o (cont.) gpio_09 i/o af26 gpio_10 i/o al33 gpio_11 i/o am33 gpio_12 i/o al34 gpio_13 i/o am34 gpio_14 i/o ak33 gpio_15 i/o ak32 gpio_16 i/o c4 gpio_17 i/o b4 gpio_18 i/o b3 gpio_19 i/o a3 gpio_20 i/o h8 gpio_21 i/o c3 gpio_22 i/o k10 gpio_23 i/o d4 gpio_24 i/o e4 gpio_25 i/o j9 gpio_26 i/o d2 gpio_27 i/o c2 gpio_28 i/o d1 gpio_29 i/o c1 gpio_30 i/o e2 gpio_31 i/o e3 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 2 of 9)
36 of 47 july 19, 2007 idt 89hpes48t12 data sheet jtag_tck i k26 test jtag_tdi i c31 jtag_tdo o j25 jtag_tms i d30 jtag_trst_n i c32 msmbaddr_1 i a31 smbus interface msmbaddr_2 i b31 msmbaddr_3 i b30 msmbaddr_4 i c30 msmbclk i/o g27 msmbdat i/o h26 msmbsmode i a32 system nc see table 22 for a listing of no connect pins. p01mergen i al2 system p23mergen i am1 p45mergen i al3 p67mergen i am2 p89mergen i al5 p1011mergen i am4 pe0rn00 i t30 pci express interface pe0rn01 i r30 pe0rn02 i n30 pe0rn03 i m30 pe0rp00 i t31 pe0rp01 i r31 pe0rp02 i n31 pe0rp03 i m31 pe0tn00 o t33 pe0tn01 o r33 pe0tn02 o n33 pe0tn03 o m33 pe0tp00 o t34 pe0tp01 o r34 pe0tp02 o n34 pe0tp03 o m34 pe1rn00 i k30 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 3 of 9)
37 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe1rn01 i j30 pci express interface (cont.) pe1rn02 i g30 pe1rn03 i f30 pe1rp00 i k31 pe1rp01 i j31 pe1rp02 i g31 pe1rp03 i f31 pe1tn00 o k33 pe1tn01 o j33 pe1tn02 o g33 pe1tn03 o f33 pe1tp00 o k34 pe1tp01 o j34 pe1tp02 o g34 pe1tp03 o f34 pe2rn00 i e28 pe2rn01 i e27 pe2rn02 i e25 pe2rn03 i e24 pe2rp00 i d28 pe2rp01 i d27 pe2rp02 i d25 pe2rp03 i d24 pe2tn00 o b28 pe2tn01 o b27 pe2tn02 o b25 pe2tn03 o b24 pe2tp00 o a28 pe2tp01 o a27 pe2tp02 o a25 pe2tp03 o a24 pe3rn00 i e22 pe3rn01 i e21 pe3rn02 i e19 pe3rn03 i e18 pe3rp00 i d22 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 4 of 9)
38 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe3rp01 i d21 pci express interface (cont.) pe3rp02 i d19 pe3rp03 i d18 pe3tn00 o b22 pe3tn01 o b21 pe3tn02 o b19 pe3tn03 o b18 pe3tp00 o a22 pe3tp01 o a21 pe3tp02 o a19 pe3tp03 o a18 pe4rn00 i w5 pe4rn01 i y5 pe4rn02 i ab5 pe4rn03 i ac5 pe4rp00 i w4 pe4rp01 i y4 pe4rp02 i ab4 pe4rp03 i ac4 pe4tn00 o w2 pe4tn01 o y2 pe4tn02 o ab2 pe4tn03 o ac2 pe4tp00 o w1 pe4tp01 o y1 pe4tp02 o ab1 pe4tp03 o ac1 pe5rn00 i ae5 pe5rn01 i af5 pe5rn02 i ah5 pe5rn03 i aj5 pe5rp00 i ae4 pe5rp01 i af4 pe5rp02 i ah4 pe5rp03 i aj4 pe5tn00 o ae2 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 5 of 9)
39 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe5tn01 o af2 pci express interface (cont.) pe5tn02 o ah2 pe5tn03 o aj2 pe5tp00 o ae1 pe5tp01 o af1 pe5tp02 o ah1 pe5tp03 o aj1 pe6rn00 i ak7 pe6rn01 i ak8 pe6rn02 i ak10 pe6rn03 i ak11 pe6rp00 i al7 pe6rp01 i al8 pe6rp02 i al10 pe6rp03 i al11 pe6tn00 o an7 pe6tn01 o an8 pe6tn02 o an10 pe6tn03 o an11 pe6tp00 o ap7 pe6tp01 o ap8 pe6tp02 o ap10 pe6tp03 o ap11 pe7rn00 i ak13 pe7rn01 i ak14 pe7rn02 i ak16 pe7rn03 i ak17 pe7rp00 i al13 pe7rp01 i al14 pe7rp02 i al16 pe7rp03 i al17 pe7tn00 o an13 pe7tn01 o an14 pe7tn02 o an16 pe7tn03 o an17 pe7tp00 o ap13 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 6 of 9)
40 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe7tp01 o ap14 pci express interface (cont.) pe7tp02 o ap16 pe7tp03 o ap17 pe8rn00 i e16 pe8rn01 i e15 pe8rn02 i e13 pe8rn03 i e12 pe8rp00 i d16 pe8rp01 i d15 pe8rp02 i d13 pe8rp03 i d12 pe8tn00 o b16 pe8tn01 o b15 pe8tn02 o b13 pe8tn03 o b12 pe8tp00 o a16 pe8tp01 o a15 pe8tp02 o a13 pe8tp03 o a12 pe9rn00 i e10 pe9rn01 i e9 pe9rn02 i e7 pe9rn03 i e6 pe9rp00 i d10 pe9rp01 i d9 pe9rp02 i d7 pe9rp03 i d6 pe9tn00 o b10 pe9tn01 o b9 pe9tn02 o b7 pe9tn03 o b6 pe9tp00 o a10 pe9tp01 o a9 pe9tp02 o a7 pe9tp03 o a6 pe10rn00 i g5 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 7 of 9)
41 of 47 july 19, 2007 idt 89hpes48t12 data sheet pe10rn01 i h5 pci express interface (cont.) pe10rn02 i k5 pe10rn03 i l5 pe10rp00 i g4 pe10rp01 i h4 pe10rp02 i k4 pe10rp03 i l4 pe10tn00 o g2 pe10tn01 o h2 pe10tn02 o k2 pe10tn03 o l2 pe10tp00 o g1 pe10tp01 o h1 pe10tp02 o k1 pe10tp03 o l1 pe11rn00 i n5 pe11rn01 i p5 pe11rn02 i t5 pe11rn03 i u5 pe11rp00 i n4 pe11rp01 i p4 pe11rp02 i t4 pe11rp03 i u4 pe11tn00 o n2 pe11tn01 o p2 pe11tn02 o t2 pe11tn03 o u2 pe11tp00 o n1 pe11tp01 o p1 pe11tp02 o t1 pe11tp03 o u1 perefclkn0 i v28 perefclkn1 i g18 perefclkn2 i u7 perefclkn3 i ah17 perefclkp0 i u28 signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 8 of 9)
42 of 47 july 19, 2007 idt 89hpes48t12 data sheet perefclkp1 i g17 pci express interface (cont.) perefclkp2 i v7 perefclkp3 i ah18 perstn i b32 system refclkm i ah8 pci express interface rsthalt i ap3 system ssmbaddr_1 i c34 smbus interface ssmbaddr_2 i c33 ssmbaddr_3 i d33 ssmbaddr_5 i d32 ssmbclk i/0 h28 ssmbdat i/o j27 swmode_0 i an4 system swmode_1 i ap4 swmode_2 i an5 swmode_3 i am5 v dd core, v dd ape, v dd io, v dd pe , v tt pe see table 20 for a listing of power pins. v ss see table 21 for a listing of ground pins. signal name i/o type location signal category table 23 89pes48t12 alphabetical signal list (part 9 of 9)
43 of 47 july 19, 2007 idt 89hpes48t12 data sheet pes48t12 pinout ? top view 1 2 3 4 5 6 7 8 9 10111213141516 vss (ground) v dd core (power) a b v dd i/o (power) 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af v tt pe (power) v dd pe (power) v dd ape (power) signals 27 28 29 30 31 32 33 34 ag ah aj ak al am an ap a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap 1 2 3 4 5 6 7 8 9 10111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 no connect x x x x x x x xx x x x x x x xx x x x x x x xx x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x xx xx x x xx xx x x xx x x x x x x x x x x x x x x x x x x x x x x
44 of 47 july 19, 2007 idt 89hpes48t12 data sheet pes48t12 package drawing ? 1156-pin bl1156/br1156
45 of 47 july 19, 2007 idt 89hpes48t12 data sheet pes48t12 package drawing ? page two
46 of 47 july 19, 2007 idt 89hpes48t12 data sheet revision history july 19, 2007 : initial publication of data sheet.
47 of 47 july 19, 2007 idt 89hpes48t12 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89hpes48t12zabl 1156-ball fcbga package, commercial temperature 89hpes48t12zabr 1156-ball rohs fcbga package, commercial temperature 89hpes48t12zabli 1156-ball fcbga package, industrial temperature 89HPES48T12ZABRI 1156-ball rohs fcbga package, industrial temperature nn aaaa nnan aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product 1156-ball fcbga bl 48t12 48-lane, 12-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character 1156-ball fcbga, rohs br aa device revision za za revision i industrial temperature (-40 c to +85 c ambient)

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